Many of today's electronic devices (e.g. cell phones, computers, personal digital assistants (PDA's), etc.) require high frequency clock signals in order to operate. Usually, these clock signals are generated using phase locked loops (PLL's).
A typical PLL comprises a phase detector, a loop filter, a charge pump, and a voltage controlled oscillator (VCO). While all of the components perform vital functions, it is really the VCO that is at the heart of the PLL because it is the VCO that provides the output high frequency signals, and it is the VCO that enables the frequencies of the output signals to be adjusted based upon a control voltage signal.
In designing a PLL, one of the starting points is the selection of an output frequency/control voltage value for the VCO. This value, referred to herein as KVCO, specifies how much the output frequency of the VCO will change given a change in control voltage. A sample KVCO plot is shown in FIG. 1, wherein the control voltage is shown along the X axis and the output frequency is shown along the Y axis. The KVCO value is given by the slope of the plot. Since the plot in FIG. 1 is a straight line, the KVCO value is a constant. In practice, the KVCO will most likely vary with the control voltage and hence, would not be a constant. Nonetheless, to simplify the design process, a constant KVCO value is used as an approximation. After the KVCO value is selected, it is used to determine the parameters of the other PLL components. In this manner, the PLL is designed around the VCO.
The KVCO value that is selected for a PLL depends upon the particular VCO that is to be used. For the particular VCO, there will be a variety of KVCO values that can be selected. This variety results not from any defect in the design of the VCO, but rather from the processing variations that are encountered in fabricating the VCO.
More specifically, a VCO comprises a plurality of components (e.g. transistors). These components are manufactured by some fabrication process. Ideally, the fabrication process should produce identical components (components with the same parameters) each and every time. In practice, however, this is not possible. As a result, there will be some variation in the parameters of the components used to make up the VCO. Some of the components will have parameters that barely meet minimum specifications, while other components will meet or exceed the maximum specifications, while other components will fall somewhere in between. Because of these processing variations, the KVCO values exhibited by different VCO's will differ, even if the VCO's are all of the identical design. This means that in selecting a KVCO value, a PLL designer has to select a value that all of the VCO's will be able to minimally achieve, which typically means that the designer has to choose the worst case KVCO value.
FIG. 2 shows some sample KVCO plots for a VCO, to illustrate the various possible KVCO values that can be exhibited by different VCO's of the same design. In FIG. 2, the KVCO1 plot shows the KVCO value for the worst case scenario (where the components of the VCO meet minimum specifications), the KVCO3 plot shows the KVCO value for the best case scenario (where the components meet the maximum specifications), and the KVCO2 plot shows the KVCO value for the typical case. As can be seen, the worst case scenario plot KVCO1 has the steepest slope. As noted above, a PLL designer typically has to select the worst case scenario to ensure that the PLL will work for all of the different VCO's of the same design. This, in turn, means that the designer has to choose the highest KVCO value (the plot KVCO1 with the steepest slope).
Using such a high KVCO value is problematic in many implementations, however. To elaborate, the KVCO value indicates how much the output frequency of the VCO will change given a change in control voltage. With a large KVCO value, even a small change in control voltage will cause a significant change in output frequency. This in turn means that if the control voltage has any noise components, those noise components will cause significant fluctuations (referred to herein as “jitter”) in the output frequency. This jitter is highly undesirable as it can cause some devices to operate improperly. Thus, using a large KVCO value in the design of a PLL has significant drawbacks.